On Aug 8, 8:09 am, jb-electronics <webmas...@jb-electronics.de> wrote: > Nick, > > > Due to internal capacitances inherent in all transistor types, > > negative going pulses will be induced [...] > > Do you really mean capacitance and not inductance? I do not see how > capacitors would "induce" and kind of voltage. Or do you mean the > capacitors' parasitic inductances?
No - its all to do with the FET and I really mean capacitance - there are parasitic capacitances between the gate, drain & source of a FET - these couple the switching transients back to the gate, where they can cause problems for I/O ports. FET driver chips are specifically designed to be protected against these transients - I/O ports of uPs generally are not. You may get away with it. You may not. The key FET capacitance modelling parameters are: Cgs is the capacitance between gate & source. Cgd is the capacitance between gate & drain. Cds is the capacitance between drain & source. Your FET data sheets quote: Ciss which is Cgs in parallel with Cgd Coss which is Cds in parallel with Cgd Crss which is the same as Cgd. Cgd is small compared with Cds, so Coss is almost the same as Cds You can see that Cgd and Cgs have the capability to couple EMI back to the gate. If you have a 'scope, stick it on the gate of the FET whilst its generating 180V under load. Correct engineering practice is not to "Muntz" the schematic! (*) http://en.wikipedia.org/wiki/Madman_Muntz Nick -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To post to this group, send an email to neonixie-l@googlegroups.com. To unsubscribe from this group, send email to neonixie-l+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/neonixie-l?hl=en-GB.
