> > Old-school flip-flop. It has a minimal transistor-count because back in > those days these were rather expensive and nobody cared about > power-consumption. A CMOS flop consumes zero static power but requires at > least 8 transistors to accomplish set-reset, whereas this bipolar dinosaur > uses at least 250mW static power if I did my calculations correctly. The > diodes & caps make the circuit edge-sensitive, not to mention interesting, > and a mental simulation tells me it's a falling-edge triggered. I havn't > figured-out why the -24V biasing is needed; perhaps those old transistors > were a tad too leaky ???
I'm sticking with FPGA's..... -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/86752f7a-b3a1-42a1-8da9-c25e7660e8b6%40googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
