Yes, the -24V bias is a bit of a puzzle. I think the idea was that if 1 of the transistor conducts, the other one is guaranteed to be not conducting. There would still be a Vsat voltage over the conducting transistor that might be just high enough to bring the other one in a partially conducting state?
on Nov 21, 2013, [email protected] <[email protected]> wrote:
Old-school flip-flop. It has a minimal transistor-count because back in those days these were rather expensive and nobody cared about power-consumption. A CMOS flop consumes zero static power but requires at least 8 transistors to accomplish set-reset, whereas this bipolar dinosaur uses at least 250mW static power if I did my calculations correctly. The diodes & caps make the circuit edge-sensitive, not to mention interesting, and a mental simulation tells me it's a falling-edge triggered. I havn't figured-out why the -24V biasing is needed; perhaps those old transistors were a tad too leaky ???I'm sticking with FPGA's.....--
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