On Tue, Sep 1, 2015 at 1:34 PM, Mitch <[email protected]> wrote: > > And I have a question - For the IN-18 version, would it be better to > connect all three HV5530s to the processor using separate data, latch, and > clock lines? The processor does have enough spare pins and the code changes > are trivial. > > Mitch > > > If you are using level shifters, then you will need additional hardware on all the lines. I would not bother,
There is a possible advantage to just using separate data lines, while keeping the CLK/LE/BLANK lines paralleled. You could clock out the data in 1/3 the time. But, it's a trade off when you are bit-banging the serial data. The determining factor is how fast you can shift the data, set io ports and then toggle the clk line in software. I did it all in an ISR written in AVR assember. I clock out 96 bits of buffer data into 3 chained HV5522s. The ISR fires at 4096hz off a timer. I get very smooth cross fades. I spent a lot of time optimizing those inner loops, shaving cycles wherever possible . I doubt that I could actually do it much faster if the data lines were separate. I'd now have to de-mux the data and manipulate 3 IO lines before I could toggle the clock line, All those extra cycles take time. I think you'd gain more by tweaking the code a bit, using the SPI hardware, or just by running the AVR at a higher clock rate. carl -------------------------------------------------------- Henry Carl Ott N2RVQ [email protected] -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/CAP_hP_SL7cWdbgEEymvfb%2BpLtU6JFbpqt2g5YXxNr%2BEncZDn9A%40mail.gmail.com. For more options, visit https://groups.google.com/d/optout.
