So to be clear, if you split the CLK lines into CLKA and CLKB, the serial data will go into the first HV5530. The first, third, fifth, etc HV5530's would use CLKA. The second, fourth, etc HV5530's would use CLKB. The DATA_OUT of the first HV5530 goes to the DATA_IN of the second HV5530, etc.
Since the HV5530 is falling-edge triggered, you would bring CLKB low first, then CLKA low afterwards. It doesn't matter when you bring either of these clock lines high as long as you meet the minimum high and low times (62nsec). The minimum 'spacing' between falling edges is the setup time (25ns) plus the max prop delay (100ns), or 125ns. I would recommend more than this to account for clock-skew, noise, etc. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/329832e7-0c82-42b9-ae3b-dbaecedbd6f8%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
