My current clock designs are using Xilinx FPGAs, coded in VHDL using Vivado.
Really not a sensible thing to do, except that I've always wanted to learn VHDL, and the only way to learn a new language (for me) is to have a decent project or two. I started clocks on discrete logic, moved to PICs, then AVRs, then MSP430s and now FPGAs...though I suspect I'll revert to MSPs after this... FPGAs are really not ideal, but they are fun. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/3b4f3c30-c99b-4a99-8348-df781d6be3ce%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
