Be careful when cascading HV5532's. The datasheet does not specify a minimum propagation delay, but it DOES require a minimum hold-time of 10nsec. Even though the datasheet says you can cascade the data-out/data-in pins of multiple devices, there are no spec numbers to support this so the next-best thing is to route the clock signal in the opposite direction of the data. I suspect the minimum prop-delay of the data-out pin is at least 10nsec, but I cant prove it.
I tend to overdesign with paranoia and pessimism, so I actually use a separate clock pin for my HV5532's when I cascaded 2 of them, so there is no possibility of a timing issue as long as I sequence the clocks correctly. Also, my clock has a total of six HV5532's (I have 14 tubes) , but I dont cascade them into a single chain. Instead, I break them into 3 parallel chains and use a level-translator IC (MC14504) to shift from the 3.3V FPGA to 12V for the HV5532. It's been running flawlessly for 2-3 years now. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/08729722-6075-46b9-b05e-0b712c03bbdd%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
