For setup time, I agree the 10ns is insignificant for a 10msec period. But for hold-time, the timing analysis starts and ends on the same clock edge. A positive hold time, in this case +10nsec, means that you must hold the data_in signal stable for 10nsec after the sampling-edge of clock, which is the falling-edge for the HV5530. If the data_in signal comes from a part that propagates in, say 7nsec, you would violate the hold-time spec by (10 - 7) = 3nsec. It may not sound like a lot of time, but hold-time violations are not forgiving. You should see what we do at my day job to fix a 25psec hold-time violation.
Another less-obvious source of timing difficulty is clock-skew; if the clock-delay to the receiving part is *longer* than the clock-delay to the sending part, the resulting difference in delay (clock-skew) worsens your hold-time. A common practice is to route clock and data signals in opposite directions. As I said, I overdesign things. I've seen too many timing problems on PC boards and inside ICs causing failures that are very difficult to find and fix, so I always take the worst-possible operation for granted, and design around them. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/bc25199b-c50f-497b-b2c0-07c82270beca%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
