Thanks Andrew. On 09/23/2016 11:13 AM, Andrew Lunn wrote: >> Since the hardware requires longword alignment for its' DMA transfers, >> aligning the IP header will require a memcpy, right? > > The vf610 FEC has an SHIFT16 bit in register ENETx_TACC, which inserts > two padding bits on transmit. ENETx_RACC has the same. > > What about your hardware? >
You got me with the RTFM! >From the i.MX6DQ reference manual, bit 7 of ENET_RACC says this: "RX FIFO Shift-16 When this field is set, the actual frame data starts at bit 16 of the first word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary." Same for the i.MX6UL. I'm not sure what it will take to use this, but it seems to be exactly what we're looking for.
