| From: Raj, Ashok <ashok....@intel.com>
| Sent: Wednesday, August 9, 2017 11:00 AM
| On Wed, Aug 09, 2017 at 04:46:07PM +0000, Casey Leedom wrote:
| > | From: Raj, Ashok <ashok....@intel.com>
| > | Sent: Wednesday, August 9, 2017 8:58 AM
| > | ...
| > | As Casey pointed out in an earlier thread, we choose the heavy hammer
| > | approach because there are some that can lead to data-corruption as
| > | opposed to perf degradation.
| > Careful. As far as I'm aware, there is no Data Corruption problem
| > whatsoever with Intel Root Ports and processing of Transaction Layer
| > Packets with and without the Relaxed Ordering Attribute set.
| That's right.. no data-corruption on Intel parts :-).. It was with other
| vendor. Only performance issue with intel root-ports in the parts identified
| by the optimization guide.
Yes, I didn't want you to get into any trouble over that possible reading of
what you wrote.
Any progress on the "Chicken Bit" investigation? Being able to disable the
non-optimal Relaxed Ordering "optimization" would be the best PCI Quirk of