On Wed, 2018-03-28 at 06:53 +0000, Linus Torvalds wrote: > > > On Tue, Mar 27, 2018, 20:43 Benjamin Herrenschmidt <firstname.lastname@example.org > ing.org> wrote: > > > > > > Of course, you'd have to be pretty odd to want to start a DMA > > with a > > > read anyway - partly exactly because it's bad for performance > > since > > > reads will be synchronous and not buffered like a write). > > > > I have bad memories of old adaptec controllers ... > > *Old* adaptec controllers were likely to use the in/out instructions > for status and command data. > > Those are actually even more ordered than UC reads and writes: the > in/out instructions are not just fully ordered, but are fully > *synchronous* on x86. > > So not just doing accesses in order, but actually waiting for > everything to drain before they start executing, but they also wait > for the operation itself to complete (ie "out" will not just queue > the write, it will then wait for the queue to empty and the write > data to hit the line). > > That's why in/out were *so* slow, and why nobody uses them any more > (well, the address size limitations and the lack of any remapping of > the address obviously also are a reason).
All true indeed, though a lot of other archs never quite made them fully synchronous, which was another can of worms ... oh well. As for Adaptec, you might be right, I do remember having cases of old stuff triggering DMA on reads, it might have been "Mac" variants of Adaptec using MMIO or something... Cheers, Ben.