> Yeah so that other trick I'm talking about is also used for timing
> accuracy.
> For example, let's say I have a device with a reset bit and the spec
> says the reset bit needs to be set for at least 10us.
> This is wrong:
>       writel(1, RESET_REG);
>       usleep(10);
>       writel(0, RESET_REG);
> Because of write posting, the first write might arrive to the device
> right before the second one.

Does not write posting only concern PCI? This seems to be a different topic. 
write posting should not include write reordering...


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