On Tue, Sep 22, 2015 at 1:36 PM, Bjørn Mork <bj...@mork.no> wrote:
>
> http://download.intel.com/design/archives/processors/pro/docs/24268935.pdf
>
> Says "NoFix" for erratas 66 and 92.
Yeah, 66 and 92 do look like they could cause the apparent ordering of
accesses to be violated. That said, both of them <i>seem</i> to be
"processor had exclusive access to line A, and gave it away but ended
up still reading now-stale data".
And that's not what we use "smp_wmb()" or "smp_rmb()" to protect
against. If we did a write and then wanted to do an ordered read, we'd
use smp_mb(), which always does that barrier.
So I don't know whether either of those really merit our PPRO
workaround. Cache coherency is hard.
There's also errata 41, which looks like it would be a bad situation.
Linus
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