Thanks Daniel. 1) Assembly syntax is great, but then it requires translation efforts to generate vhdl/verilog output. And more effort to verify efficacy of manual translation. Most HDL tools support c like syntax then it's easier to use for verilog/vhdl as they have language support. That's all.
2) My mistake,in my vhdl implementation context backward jump is like for e.g. ldh[12]...few other instruction..ldh[10], as access to 10 comes after location 12 is accessed. What it does is you can't create parallel state machine. Even though jumps on jt/jf is forward direction. Hope this clarifies my previous vague statement. so far i understood from bpfc notes and messages is that, it basically binds filter to the specified socket, does that mean it doesn't do in-place filtering?if yes then what is the performance advantage and how it gains that performance advantage?i will be looking deep into bpfc, any knowledge sharing of natural language(tcpdump filter definition options for e.g.) to CFG generation will be great Daniel. On Thursday, September 19, 2013 3:12:07 PM UTC-4, chintu hetam wrote: > > Hi All, > > I am looking on implementing HW filters using bpfc. > > This is a process outline > > 1) Generate BPF file in human readable format -> How to use BPFC to > generate human readable format(labels etc.)..? > 2) parse and check for (if any backward jumps and correct the sequence) > 3) Generate VHDL state machine > > Also,i was not able to generate JIT or C o/p using bpfc..any help is more > than welcome > > Cheers > r2r > > -- You received this message because you are subscribed to the Google Groups "netsniff-ng" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
