On 12/3/25 12:59 PM, Timur Tabi wrote:
On Tue, 2025-12-02 at 21:59 -0800, John Hubbard wrote:
+ // Read GSP falcon mailbox0
+ *mbox0 = gsp_falcon.read_mailbox0(bar);
+
+ // Check 1: If mbox0 has 0xbadf4100 pattern, GSP is still locked down
+ if *mbox0 != 0 && (*mbox0 & 0xffffff00) == 0xbadf4100 {
+ return false;
+ }
Isn't this effectively triggering a PRI exception, because the register cannot
be read and that's
why it's returning BADF?
Ah no, this is a PRI *error code*, rather than an actual PRI exception.
From Open RM:
#define GPU_READ_PRI_ERROR_MASK 0xFFF00000
#define GPU_READ_PRI_ERROR_CODE 0xBAD00000
...and:
//
// HW will return 0xbad in the upper 3 nibbles
// when there is a possible issue.
//
if ((value & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE)
{
gpuHandleSanityCheckRegReadError_HAL(pGpu, addr, value);
}
And in this case, it's just part of expected normal operation
while waiting for GSP to get done with "lockdown mode" (which
it is in while booting up).
Here's the Open RM code for reference:
static NvBool
_kfspIsGspTargetMaskReleased
(
OBJGPU *pGpu,
void *pVoid
)
{
const NvU32 privErrTargetLocked = 0xBADF4100U;
const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it
has extra error information
NvU32 reg;
//
// This register is read with GPU_REG_RD32_UNCHECKED to avoid the 0xbadf
sanity checking
// done by the usual register read utilities.
//
reg = GPU_REG_RD32_UNCHECKED(pGpu, DRF_BASE(NV_PGSP) +
NV_PFALCON_FALCON_HWCFG2);
return ((reg != 0) && ((reg & privErrTargetLockedMask) !=
privErrTargetLocked));
}
thanks,
--
John Hubbard
