The NV_PFALCON_FALCON_DMATRFBASE/1 register pair supports DMA addresses up to 49 bits only, but the write to DMATRFBASE1 could exceed that. To mitigate, check first that the DMA address will fit.
Reviewed-by: John Hubbard <[email protected]> Reviewed-by: Joel Fernandes <[email protected]> Fixes: 69f5cd67ce41 ("gpu: nova-core: add falcon register definitions and base code") Signed-off-by: Timur Tabi <[email protected]> --- v2: Improved comment and moved check earlier in function drivers/gpu/nova-core/falcon.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 82c661aef594..6ae0490caffa 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -472,6 +472,12 @@ fn dma_wr<F: FalconFirmware<Target = E>>( return Err(EINVAL); } + // The DMATRFBASE/1 register pair only supports a 49-bit address. + if dma_start > kernel::dma::DmaMask::new::<49>().value() { + dev_err!(self.dev, "DMA address {:#x} exceeds 49 bits\n", dma_start); + return Err(ERANGE); + } + // DMA transfers can only be done in units of 256 bytes. Compute how many such transfers we // need to perform. let num_transfers = load_offsets.len.div_ceil(DMA_LEN); base-commit: 2d7b4a44fb768e1887e7e4cdd8b86817ccd9c3bf -- 2.52.0
