[PATCH v2 02/15] cxl/core: Track port depth

[Ben Widawsky]

Signed-off-by: Ben Widawsky <ben.widaw...@intel.com>
---
 drivers/cxl/core/port.c | 7 ++++++-
 drivers/cxl/cxl.h       | 2 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 5a1ffadd5d0d..ecab7cfa88f0 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -436,13 +436,18 @@ struct cxl_port *devm_cxl_add_port(struct device *host, 
struct device *uport,
 {
        struct cxl_port *port;
        struct device *dev;
-       int rc;
+       int rc, depth = parent_port ? parent_port->depth + 1 : 0;
 
        port = cxl_port_alloc(uport, component_reg_phys, parent_port);
        if (IS_ERR(port))
                return port;
 
+       if (dev_WARN_ONCE(&port->dev, parent_port && !depth,
+                         "Invalid parent port depth\n"))
+               return ERR_PTR(-ENODEV);
+
        port->host = host;
+       port->depth = depth;
        dev = &port->dev;
        if (is_cxl_memdev(uport))
                rc = dev_set_name(dev, "endpoint%d", port->id);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 276b93316e7f..6eeb82711443 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -272,6 +272,7 @@ struct cxl_walk_context {
  * @decoder_ida: allocator for decoder ids
  * @component_reg_phys: component register capability base address (optional)
  * @dead: last ep has been removed, force port re-creation
+ * @depth: How deep this port is relative to the root. depth 0 is the root.
  */
 struct cxl_port {
        struct device dev;
@@ -283,6 +284,7 @@ struct cxl_port {
        struct ida decoder_ida;
        resource_size_t component_reg_phys;
        bool dead;
+       unsigned int depth;
 };
 
 /**
-- 
2.34.1