[PATCH v3 37/40] tools/testing/cxl: Fix root port to host bridge assignment

[Dan Williams]

Mocked root-ports are meant to be round-robin assigned to host-bridges.

Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port 
hierarchy")
Signed-off-by: Dan Williams <dan.j.willi...@intel.com>
---
 tools/testing/cxl/test/cxl.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index cd2f20f2707f..7e4a0b1ee436 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -558,7 +558,7 @@ static __init int cxl_test_init(void)
 
        for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {
                struct platform_device *bridge =
-                       cxl_host_bridge[i / NR_CXL_ROOT_PORTS];
+                       cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];
                struct platform_device *pdev;
 
                pdev = platform_device_alloc("cxl_root_port", i);