On Tue, Apr 26, 2022 at 5:31 PM An Sarpal <[email protected]> wrote: > > Dan, thank you. > > Yes that is true but PCIe memory (assuming a PCIe BAR is backed by real > memory and not just registers) never participated in cache coherence anyways. > So assuming my applications using /dev/dax0.0 character device were aware of > this feature (or lack of it), would this implementation be the correct way to > do it?
It does not matter if the BAR is backed by real memory. It is incoherent with other initiators on the bus, so it can create cases where dirty data is stranded in CPU caches while a another bus initiator tries access the same physical address.
