This series can be found here:

        https://github.com/weiny2/ndctl/tree/dcd-region3-2025-04-13

CXL Dynamic Capacity Device (DCD) support is being discussed in the
upstream kernel.  cxl-cli requires modifications to interact with those
devices.

A new partition type 'dynamic_ram_a' has been added which cxl-cli
needs to know about.  Add support for the new decoder type.

With DCD regions may, or may not, have capacity.  The capacity is
communicated via extents.  Add region extent query capabilities.

Add cxl-test support.  cxl-testing allows for quick regression testing
as well as helping to design the cxl-cli interfaces.

Signed-off-by: Ira Weiny <ira.we...@intel.com>
---
Changes in v5:
- iweiny: Adjust all code to view only the dynamic RAM A partition
- Alison: s/tag/uuid/ in region query extent output
- Link to v4: 
https://patch.msgid.link/20241214-dcd-region2-v4-0-36550a97f...@intel.com

---
Ira Weiny (5):
      libcxl: Add Dynamic RAM A partition mode support
      cxl/region: Add cxl-cli support for dynamic RAM A
      libcxl: Add extent functionality to DC regions
      cxl/region: Add extent output to region query
      cxl/test: Add Dynamic Capacity tests

 Documentation/cxl/cxl-list.txt   |  29 ++
 Documentation/cxl/lib/libcxl.txt |  33 +-
 cxl/filter.h                     |   3 +
 cxl/json.c                       |  67 +++
 cxl/json.h                       |   3 +
 cxl/lib/libcxl.c                 | 181 ++++++++
 cxl/lib/libcxl.sym               |   9 +
 cxl/lib/private.h                |  14 +
 cxl/libcxl.h                     |  21 +-
 cxl/list.c                       |   3 +
 cxl/memdev.c                     |   4 +-
 cxl/region.c                     |  27 +-
 test/cxl-dcd.sh                  | 863 +++++++++++++++++++++++++++++++++++++++
 test/meson.build                 |   2 +
 util/json.h                      |   1 +
 15 files changed, 1253 insertions(+), 7 deletions(-)
---
base-commit: 507cdf47bab05e148086ef6b7e3aad278d051f14
change-id: 20241030-dcd-region2-2d0149eb8efd

Best regards,
-- 
Ira Weiny <ira.we...@intel.com>


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