On Thursday 10 February 2005 00:43, Daniel Phillips wrote: > On Wednesday 09 February 2005 18:30, Lourens Veen wrote: > > Replying to self due to sudden brainwave: 36 = 18 + 9 + 9. Let's > > assume we take two RAM blocks. An extra RAM block will improve > > performance a lot, and there are 40 of them, so I'd say we can afford > > it. > > Hi Lourens, > > Saving a clock here doesn't improve performance because it's pipelined > anyway. A single, dual-ported 18 Kbit table can do the job in a total > of two clocks for two pixels. Not only is it perfectly efficient, it's > also about as simple as you can get.
No it doesn't. Let's assume that we have eight pixels numbered p0-p7. We process two at a time, and need one RAM read per stage per pixel. If we use a two stage (st0, st1) pipelined implementation and a single 1024x18 RAM table the following happens: clock st0 st1 0 rd0 - 0 rd1 - 1 rd2 rd0 1 rd3 rd1 2 rd4 rd2 2 rd5 rd3 3 rd6 rd4 3 rd7 rd5 4 - rd6 4 - rd7 Four reads per clock. What pipelining does is allow you to chop up complex operations that take a long time to complete into small bits that take a shorter time to complete. This increases throughput, and it allows higher clock rates, but you still need all the work. In this case, we need two reads per pixel, so if we want to spit out two pixels each clock we need four reads per clock. No amount of pipelining can change that. Lourens _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
