> This will deliver 2 pixels/clock most of the time, but will stall up to > 3 clocks on short spans. Worst case is to fill the screen with single > pixel vertical strips, which will cut the fill rate by 75%. Typical > throughput reduction should be much less, perhaps in the 5-10% range. > If there really are four multipliers left over, they could be applied > to cutting the span setup stall to a single clock.
What about separate FPGA flashes for speed and correctness? This thought is not new, but I think it's been a while since it was considered and discussed. This FPGA will be reprogrammable, that will pretty much guarantee that flashable mods will appear (if design is Open Source). But what about having two "official" designs that the user can choose and trust depending on his needs. The default one should be profiled for image correctness, and thus may sacrifice speed in favor of extra processing for quality. (ex: extra precision) The alternative should be profiled for speed with acceptable quality losses. This (i hope) would allow the design to free up transistors that can be used for increasing overall speed instead. (ex: extra pipelining to allow higher clock) Since the default is slow but pretty I think nobody would complain about quality decrease if they themself choose to change the profile to favor speed. This would allow once-a-week gamers to get that extra punch when they try to frag their fellow CAD designers. Yes it'll be extra work, but optimizing for both profiles in one core may be more frustrating and lead to unneeded sacrifices. Thoughts? -HK _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
