I'm a little confused.  Are you using two tables to compute only one
reciprocal?  Can you also compute another reciprocal at the same time?

On Tue, 15 Feb 2005 17:17:19 +0100, Lourens Veen
<[EMAIL PROTECTED]> wrote:

> 
> Be sure to try every possible input for the mantissa. It gets interesting...
> 
> Here's my latest attempt. It gives an 18-bit mantissa, with maximum errors -0
> and +1. That is +2**-18 in your notation I think. Rounding by adding 0x3E and
> truncating is just lucky. If you add 0x3D or 0x3F the maximum error becomes
> one larger (or twice as big, depending on how you look at it).
> 
> I've also written it in a sort of hardware style, which makes it easier to
> find out how much hardware we need. Here's the list assuming 1 + 8 + 16
> float25 (probably in more detail than is realistic for an FPGA, but what the
> heck):
> 
> * For the mantissa
> 2 1024x18 tables
> 8 XOR gates
> 1 NOT gate
> 1 AND gate
> 3 2x11 MUXes
> 1 9 + 11 -> 12 adder
> 1 2 + 11 -> 12 adder
> 1 14 + 16 -> 11 adder (drops the 6 least significant bits)
> 1 18 + 11 -> 18 adder (drops the most significant bit, and the least
> significant bit as well if we truncate to 17 bits)
> 
> * For the exponent (not in the attached code)
> 8 NOT gates
> Something that subtracts 2 from (or adds 254 to) an 8-bit number
> 
> I think it would be 3 stages, plus 4 times whatever you need for an adder.
> These adders are a bit simpler than the full adders Timothy posted a little
> while ago, so maybe they'll fit into 3 stages, making a total of 15 stages.
> But we don't care about latency anyway.
> 
> Cheers,
> 
> Lourens
> 
> 
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