On Thu, 24 Feb 2005 00:07:16 +0100, Attila Kinali <[EMAIL PROTECTED]> wrote:
> On Tue, 22 Feb 2005 09:54:55 -0500
> Timothy Miller <[EMAIL PROTECTED]> wrote:
> 
> > On the FPGA board, the PCI controller will probably be separate.  But
> > in the ASIC, we'll simply glue the two units together with a
> > minimalist wrapper so as not to disturb the design of either one.
> 
> I just had a thought about this again. Wouldn't it be better
> to keep the PCI interface in the FPGA and instead use a
> JTAG interface ? Then an additional (semi)custom chip could be
> saved, the whole board would be debuggable and still easily
> programmable. Additionaly, you could use the same PCB
> for the ASIC and the FPGA version as they would not
> differ in their functionality, which brings the FPGA
> board a big step nearer to the price of the ASIC board.
> 
> As an interface, either an special JTAG interface card
> or some adapter to the parallel port could be used.
> Those who'd like to play with these features will
> for sure not mind if they have to connect a cable
> from outside to the board.
> 
> The only thing i'm not sure about is, how the
> pins of an FPGA react while programming, ie
> whether they could lock up the PCI bus or something.

This was all a major factor when we were assuming that the primary
product would be based on an FPGA.  Now that we've given ourselves
more freedom, we can change the FPGA design so that it's easier for
experimenters to use.

Note that the NRE for the ASIC is so huge that it absolutely dominates
everything else.  Nothing else even comes close.  What we want to do
is design an FPGA board that is relatively large and has lots of test
points for debugging, while the ASIC board is small and inexpensive. 
Sometimes you spend a little more now in order to insulate yourself
against catastropic expenses in the future.  Spending $100k extra now
in order to ensure that we don't have to spend another $1 million on
an ASIC respin is well worth the cost.
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