On Friday 25 February 2005 07:53, Timothy Miller wrote:
> the basic idea is, "What do you do when you write to an
> address that's represented in a read cache?"  Simple answer:  Whenever
> you're going to read something you may have written to, flush the read
> caches.

Flushing the read caches in itself isn't enough because we also have to 
worry about write-read ordering.  If ReadPixels operates independently of 
the rendering pipeline, we need to synchronize it somehow.  The easiest way 
is to flush the pipeline, either explicitly with a graphics command as 
Nicolai suggested or implicitly with dedicated logic.

On the other hand, it would be easy to make ReadPixels use the graphics 
pipeline, which gets rid of the race in a rather expensive way.  But it 
would still be fast enough to saturate the PCI bus.

Regards,

Daniel
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