On Fri, 18 Mar 2005 10:49:59 +0100, Attila Kinali <[EMAIL PROTECTED]> wrote: > On Thu, 17 Mar 2005 23:31:45 -0500 > Timothy Miller <[EMAIL PROTECTED]> wrote: > > > I wasn't clear. When I say that the GPU "polls the write pointer", I > > mean, "the GPU does a DMA read of a word in host memory that contains > > the write pointer". > > The pointer here is a 64 bit value, right ? > How do you garantee atomicity of the read ? > Ie i see here a race condition on 32 bit systems, > when the host updates the pointer.
This "pointer" is really just an index into the ring buffer and is therefore much smaller than 32 bits. > > And how does it work with cache ? Ie, is the cache > flushed if the pci buss accesses a region of the > host memory which contents were modified in the cache ? That is a separate issue. Linux and other OS's have kernel functions that must be used to sync DMA buffers so that devices don't get old data. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
