In the case where we have run out of multipliers and need more, we can either code our own (as you have done), or tell the synthesis tool to infer one in random logic with however many stages of pipeline that we want.


On Apr 4, 2005 12:46 PM, Hans Petter Selasky <[EMAIL PROTECTED]> wrote:
Hi,

How much does the multiplication circuits impact on price/power/heat/speed?

Will it be worth optimizing multiplication like this (in FPGA, expanding the
while loop):

/*
* multiplication without having to
* wait for the carry to complete
*/
u_int32_t
multiply_1(u_int32_t a, u_int32_t b, u_int32_t remainder)
{
        u_int32_t carry = 0;
        u_int32_t temp = remainder;
        u_int32_t old;

        /* step 1
         * convert b into a
         * +-0+00-0+- string
         * which is parity
         */

        b ^= 2*b;

        /* step 2
         * multiply
         */
        while(b)
        {
                if(b & 1)
                {
                        old = carry;
                        carry = temp;
                        temp = a | old;
                }

                temp ^= carry;
                carry &= temp;

                /*
                 * new carry is 0 under temp == 1.
                 * That is why (a | old) is possible.
                 */

                b /= 2;
                a *= 2;
                carry *= 2;
                temp *= 1;
        }

        /* step 3
         * subtract rest of carry
         */
        temp -= carry;

        return temp;
}

Please CC me,  hence I'm not on the list.

Yours
--HPS
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)

_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)

Reply via email to