The prototype board will be broken down into these components:

- Four 256 megabit DDR SDRAM chips
- DVI, DAC, TV, and other video chips
- Misc (voltage regulators, etc)
- PROM
- A Xilinx Spartan III 4000 or a 1500 (two product models)
- A Lattice XP6 flash-based FPGA for the host interface

I'm probably leaving something out, but the important bit here is that
last part.  We want an instant-on device for PCI.  It's separated out
so that it can serve as a PROM interface and also as a loader for the
Xilinx.  One PROM chip will hold both the BIOS and the Xilinx bitfile.

For the 3S1500-based board, the PCI controller could actually be quite
trivial.  Only the 3S4000-based board can be used for OGP, so the 1500
model is only for user projects.  The idea is to have a cheaper
version of the board for people who have more interest in this product
than later OGP products.  However, for the 4000-based board, we need
to have a nearly complete host interface that does all of the
interfacing that OGP will need at the time the OGP core is ready. 
This includes bus mastering/DMA, appropriately sized memory apertures
(BARs), etc.  We really only need PCI only at first.  We'll include
AGP functionality into the state machine, and later boards will have
it, but it won't matter, since the card doesn't have an AGP connector.
 We will have to produce AGP versions in small quantity.

There are going to be some special features for the prototype. 
There's one PROM for BIOS and bitfile.  You'll need to be able to
reprogram those.  You're also going to want to be able to get the
Xilinx to reload.  Finally, you're going to want to be able to
soft-program the FPGA (without touching the PROM).  I am proposing
that we make use of some of the extra config space register for this. 
There'll be some address/data pairs that you use to indirectly get at
those things.  The problem with that approach is that it may be very
slow, especially if you have to do an ioctl per access to config
space.  Anyone want to comment on this?

Additionally, here's a tentative set of BARs for memory-mapping:

- 128K space for control aperture
- 128M space for graphics memory
- (undetermined) space for user (prototype only)
- (undetermined) space, possibly for write access to PROM


(Sorry for the ramble.  This is what happens in the afternoon
blood-sugar low. :)

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