On 5/28/05, Viktor Pracht <[EMAIL PROTECTED]> wrote: > Am Samstag, den 28.05.2005, 12:49 -0400 schrieb Timothy Miller: > > > > Now for the math. Timothy said to expect a 20 clock delay for random > > > access to card memory. I'm going to assume that is 20 clocks in the > > > 200Mhz domain. > > > > No. I'm assuming a large part of that delay comes from synchronizing > > FIFOs between clock domains. > > Why does the VGA controller have to run at a different clock rate than > the memory controller?
Easier to design, uses less logic. I'm targetting 200MHz for the rendering core, but to do that, it's MASSIVELY pipelined. It makes the P4 pipeline look tiny. The only reason that's okay is that, for the most part, an earlier stage in the pipeline is not dependent on a later one. But we're designing a CPU here, with lots of cyclic dependencies. Pipelining it to run at 200MHz is very unlikely to help. > > > Furthermore, I'm assuming a row miss in > > the memory controller, and numberous other delays. > > Can the VGA controller get a more direct access to the cache and/or > VRAM? Direct enough to be able to predict when the results of a read > arrive? No. The memory controller is a central resource with lots of different things trying to access it all at once. Consider, for instance, the main video controller. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
