> On 5/27/05, Alexander van Heukelum <[EMAIL PROTECTED]> wrote: >> On Thu, 26 May 2005 13:51:11 -0400 >> Timothy Miller <[EMAIL PROTECTED]> wrote: > We could make some sort of SIMD logic for the translation that's > controlled by the processor. But I think we can absorb the latency by > splitting read instructions. >
One of the easy technique for splitting is to use special register like cdc6600. You write an address in a register and you load the value from an other one. So you could put many instruction between the 2 last one. Nicolas Boulay _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
