On 5/31/05, Chip Bilbrey <[EMAIL PROTECTED]> wrote: > On Tue, 2005-05-31 at 09:26 -0400, Timothy Miller wrote: > > What are your pipeline stages? I'm thinking there's: > > - fetch > > - read > > - compute > > - write > > I assume he's referring to a classic 5-stage design with a MEM stage: > -fetch > -decode > -execute > -memory access > -register writeback
With our load/store architecture, memory access is nothing more than tossing things into fifos, and that's done in the execute stage. Also, memory accesses are the only "locks" in the pipeline. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
