On Sun, Jun 12, 2005 at 09:53:49PM -0400, Timothy Miller wrote:
>
> Something in the back of my mind is telling me that there are <<< and
> >>> operators in either VHDL or Verilog, but I cannot remember what
> they do... and google chokes on that.
As it happens, I had the Palnitkar textbook open to the page that
defines those operators. They're arithmetic shift left and right. That
doesn't seem to be what you want here.
I didn't look at your code long enough to do it justice, but it
looks like you're selecting a byte from a multi-byte word to put on an
output port. A multiplexer written as a case statement might be a clear and
compact way to express it.
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