On 8/14/05, Brian Magnuson <[EMAIL PROTECTED]> wrote: > * Timothy Miller <[EMAIL PROTECTED]> [2005-08-12 18:15]: > <snip> > > Things I could use help with: > > > > (1) Simulating other sorts of transactions, like memory reads and writes > > (2) Finishing other parts of what goes into the Lattice chip, like the > > PROM interface > > > > Although many of you have stayed away from this because you don't have > > access to a PCI spec, there are other parts of the design that are not > > part of that. I would like for the community to help push forward on > > that. > > > > Cool stuff, and high performance too! Who knew you could run a PCI bus at > 100THz? :)) > > Anyway, the last time I checked this project the RTL was going to be closed. > Looks like that's changed (yea!). I play at being an RTL designer by day and > would be more than happy to contribute. I was poking around the wiki and > wasn't able to find much in the way of design docs/specs. What's being worked > on? Searching the archives I found a long thread on a VGA controller but > that's about it.
Let's begin by having an open discussion about what's going into the Lattice chip. Since I have much of the PCI logic done, let's work on some of the other stuff. Two things on the plate right now: (a) SPI PROM reading and writing, and (b) how to program a Xilinx chip. We could program the Xilinx serially or using its parallel interface. Probably should go with the latter if we can get data out of the PROM fast enough. The sooner the Xilinx is online during the boot process, the better. Let's talk about the logic involved and how they're going to interface with the host controller. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
