On Wed, 14 Sep 2005 00:04:53 -0400
Timothy Miller <[EMAIL PROTECTED]> wrote:
> So, here's the solution: Of all 64 combinations, go through and
> identify which ones are meaningful and which ones are meaningless or
> redundant. Add a thin layer of logic that reduces those combinations
> to a much smaller number. Now, the state machine only has to compute
> that number of possible "next states". (Whether those states are
> numbered in binary or one-hot is something to be determined as a
> result of trying to synthesize it, but I'm going to start with
> binary.)
Whithout knowing the pci specs, i think this nummber can be
further decreased. If you draw the state machine as a graph
you'll see that there are only a limited number of edges from
one state to the next. This means, that the maximum number
of next states you'll have to compute, is the maximal degree
of a node.
Ofcourse edges that go to the same nodes should be collapsed
to decrease the degree of the nodes.
The only drawback of this system is, that we need to compute
first what states could come next from the current state,
but that could be hardcoded into a few LUTs.
Attila Kinali
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