On Fri, 21 Oct 2005 18:19:25 -0400
Timothy Miller <[EMAIL PROTECTED]> wrote:
> What I want to know about is like how many columns of how many pins at
> what spacing, like how IDE is 20 columns of 2 rows of however many
> pins. If there is some standard connector that would be appropriate
> for connecting daughter cards, we should use that. But what we use
> should also look like rows of headers, kinda like how the IDE pins
> look.
I would rather start from the other end: What for do we need
such a connector? If there is no need, do not put it in.
I know it would be cool to have one, to be able to extend
the board, to play with it. But keep in mind that everything
we add also adds cost in production. But such features
add very little value to the casual customer.
If you think we want one for future development and stuff
i would just connect the left over FPGA pins to a grid
of header pins. Though, you have to keep in mind that we
will be dealing with high frequency signals
(data clk freq*5 at least) and this will limit either
the use of the pins if we use cheap header pins or
we need to get an expensive connector with defined
wave resistance.
Attila Kinali
PS: Please, please stop top posting. It makes follwoing
discussions a lot harder.
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