Timothy Miller wrote:
On 10/22/05, Daniel Rozsnyó <[EMAIL PROTECTED]> wrote:
Does PCI provide both voltages or only the one for
> which the card is designed?
This does not matter, there can be a FDD/HDD power connector on the
"graphics" board, as could be seen on some graphic cards.
About the pins: TTL is good for simple and slow add on cards (and for
me). If the developers want a high speed interface, wouldn't it be
possible to realize it with differential signalling? Has the FPGA such
an option to drive a pair of output pins with reverse polarity?
Well, I do believe there is some sort of differential signalling that
the Xilinx can do, but I'm not sure. At the very least, you could
code your logic so that it drove pairs of pins in antiphase. But I'm
not sure if that'll solve the problem or not.
I'm working on a board that is using LVDS signals and a Spartan3 at the
moment, and I was asked if we could just hook up the spare IO to a
differential connector to allow daughter boards, so I'll outline some of
my discoveries for the benefit of the list (you may wish to
independantly verify them, it's all datasheet info, but I'm still
learning!).
Xilinx does allow for differential signalling but there are a few catches:
1. Only certain pairs are differential.
2. Differential signals must be routed correctly (trace spacing needs
to be fixed, as does trace length - means you have to think about it as
a feature, and not an afterthought)
3. High speed connectors are expensive, and standard header
connectors/ide cable may introduce too much noise into the system to
make the differential connection work.
4. You have to choose a differential standard and stick to it - because
the standard is based off Vcco/Vref in that bank. Thus, this may affect
your other devices on that bank.
On the plus side:
5. You can use the DCI feature to terminate differential lines at
compile-time, so you don't have to define inputs or outputs, you can
allow the FPGA programmer to do that for you (however it looks like only
LVDS is supported).
My recommendation, in the end, was that high-speed connections as an
after-thought was a bit more than I could implement (they also wanted to
be able to switch from using an FPGA to a connector for the same
signals) given my experience, but hooking up a bunch of standard IO to
an IDE header was not too bad (routing was a bitch, but I only had
4-layers at the time) and just requiring running traces from a bunch o'
input to the pins of an IDE header.
My biggest lesson learnt with that IDE header was to consider how to
route traces to it at schematic entry time, not routing time, while it
was easy to change the pin-to-pin connections.
I also have most of these components and sockets sourced for the UK
(uk.farnell.com, mostly) so should you need some product numbers or
ideas, I have them readily available =)
- Piete
PS: I love what you're doing, and have been following with great
interest and enthusiasm from about August! You're parallelling much of
my own work with the Spartan3 (choices on how this or that works) and
this list has been an endless source of new information! I only wish I
could offer more of my services, but I'm so untested in this field that
I'd be worried I'd get it wrong!
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