On 11/12/05, Carl Witty <[EMAIL PROTECTED]> wrote: > > Disclaimer: I haven't tried this, but I think it should work. > > Keep two counters running in parallel; one is a "normal" 5-bit counter, > and the other is a gray-encoded version of the same thing. Rather than > actually try to count in gray codes, it's probably easier to just > gray-encode the original counter on each clock. I don't remember > Verilog or VHDL syntax, but something like this, where ":=" is a > registered assignment: > > counter := prev_counter+1 > gray_counter := gray(prev_counter+1) > > (Don't do "gray_counter = gray(counter)" (unregistered), because that > might glitch as counter changes.)
That's an interesting idea. Ok, so you have a counter and also a graycode number that can be read in the other clock domain. Some things can be determined just from comparing graycode head and tail pointers. What you can then do in the other domain is register it and then convert it back to binary to get more information. The only problem I see is that this will require a lot of logic. The approach I just posted sacrifices one fifo entry in order to simplify things considerably. I'm not sure what would be the impact of the extra registers in my design, but there would probably be just as many or more extra registers in this approach. However, your suggestion could yield more information about the fifo; for instance, you could determine how many free or used entries there are, which is important for things like command fifos where full/empty is not enough information. I think that will be very useful later. > > Use bits [3:0] of counter (not gray_counter) as your address bits, and That solves one of my problems, yes. I was hoping to use the gray counter without the need for a binary counter, but maybe having both is necessary. > use gray_counter to compare with the other clock domain. When > gray_counter is equal to other_gray_counter, the FIFO is empty; when > xor(gray_counter, other_gray_counter) is equal to 24 (yes, 24, not 16), > the FIFO is full. Hey, that's cool! I didn't think of that either. You're right. When two 5-bit gray counters are exactly 180 degrees out of phase, their xor is 24. > Be sure to register the outputs of your "FIFO is empty" and "FIFO is > full" computations (and make sure your synthesis tool does not replicate > these registers); otherwise, you may run into issues where part of the > circuit acts as if the FIFO is empty and part of it does not. I've been thinking about that. I guess you're talking about a race condition where the result of the xor maybe causes metastability in one replication of the register and not in another and similar conditions. That is indeed a concern. The routing to different registers is going to be different and have potentially disasterous effects. I need to find out how to flag individual registers as nonreplicable in both Xilinx and Lattice synthesis tools. Thank you. Your suggestions were very illuminating. Have you had a look at the fifo code I posted? What do you think of that one? Thanks. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
