Am Sonntag, den 27.11.2005, 21:35 -0500 schrieb Timothy Miller: > > The FIFO has way too many states to examine them manually, so while it > > was useful for proving the existence of a race condition, it's useless > > for proving their absence. A testbench for the FIFO would really help > > here. > > I have one, but it's digital and RTL-based. We'd have to synthesize > it and run a gate-level simulation. Even then, routing delays will > vary.
I meant Verilog source for a testbench, which I can integrate into the petri net. Then it can run alone for a couple of days to test all possible states and delay combinations. - Viktor Pracht _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
