On 12/4/05, Attila Kinali <[EMAIL PROTECTED]> wrote: > On Mon, 28 Nov 2005 08:47:31 -0500 > Timothy Miller <[EMAIL PROTECTED]> wrote: > > > Actually, we're pin-limited for OGD. > > Huh? Where did all those x*100 pins go? > I know that PCI and Memory uses quite a lot, but i thought > that the rest should just need a few and thus half of the > pins would be still unused.
I'd have to let Andy answer this in detail, but we are using a heck of a lot of pins. Also, I think I posted something to the list before that detailed the pins. I'm an amateur at PCB layout, but I have paid attention to what others have done at Tech Source, and I have seen that as clock rates have gone up, pin-sharing has had to go down. We're at a point where we strive to make as many signals point-to-point as possible. So, with DDR memories, the data is, say, 400MHz. You want to make your data lines as short as possible and point-to-point. If you route your control signals (200MHz) as nicely, then you can generally get away with one pin going to two RAM chips. Also, general I/O's are actually a relatively high priority for OGD. It's a general purpose board. Given the choice between two interfaces and one with extra general I/O, I'll choose the extra general I/O. To OGA, OGD is a necessary step, but to Traversal, OGD is a product line that will persist as long as anything else. There's a market need for it. > > And yes, i know what a routing nightmare is.. > We just finished the desing of an advanced FPGA board > here that has 36 layers, 20 of which are carrying signals ^^' > No, dont ask about the costs :-/ Egad! _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
