On Tuesday 27 December 2005 18:32, Timothy Miller wrote: > On 12/27/05, Pieter Hulshoff <[EMAIL PROTECTED]> wrote: > > 4. Don't use extra FFs for logic that's already small/fast. Consider what > > kind of hardware each function will become, and decide accordingly if it > > needs to be clocked or can be used combinatorial. > > In FPGAs, they're generally free at the ends of combinatorial logic, > and this is also true for some ASICs. Could you point out a specific > example of where you made this change and how it was an improvement?
Hmm, this one for instance: full <= (next_gray_code( wr_ptr_nxt ) == rd_ptr_meta); You could choose to precode next_gray_code( wr_ptr_nxt ) and place it in a set of FFs the clock cycle before, but since an equal comparison of 4 bits really is very small, there's no need to use an extra FF. Most ASICs don't get this for free, and with FPGAs it depends a bit on what you're building. Sometimes it won't show up, and at other times it won't. I prefer not to use extra FFs unless I think it's needed for speed. All in all it really doesn't matter that much though; this FIFO is a relatively small block, so a few extra gates won't hurt that much anyway. If a function is to be used often within the design it's time to have a really good look at this; something I learned when having to use a Galois multiplier a few thousand times within a FEC design. ;) My attempt was mostly meant to get a bit of first time experience with Verilog, and to see if I properly understood the FIFO idea you had. Regards, Pieter Hulshoff -- The last good thing written in C was Franz Schubert's Symphony number 9. When your hammer is C++, everything begins to look like a thumb. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
