On 3/7/06, tsuraan <[EMAIL PROTECTED]> wrote: > > Our parts supplier assured us that this part is supported by the FREE tools. > > Good to hear. Thanks! > > > Although the tools are free, it would be interesting to have open > > source synthesis tools. > > > > Chip synthesis, is, of course, an NP-complete (or worse) problem, so I > > don't see OSS synthesis tools being right on the horizon. But perhaps > > this project will encourage some development in that eventually. > > It would be cool if that happened. From what I understand though, the > really hard part of making synthesis tools is that the structure of > the bitfiles themselves is generally not published. It would be a bit > like writing a compiler for a totally undocumented processor. The > algorithms are difficult, but that final layout step is the real > killer, from what I've read. >
Maybe the chip manufacturers will play nice. We may be able to convince them that there is revenue potential here. But even with full documentation, there's still the issue of developing good P&R. IIRC, icarus can produce EDIF netlists. I don't know if it bothers to optimize them any, but you can then feed that into P&R software and get a routed bitfile. What's really hard about this, though, is that everyone's going to physical synthesis where the P&R is combined with synthesis. Wire delays (which are dominant in modern chips) are exact, rather than estimates. When wire delay is going to affect synthesis, the syntesizer can take it into account and do a better job optimizing. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
