On Tuesday 18 April 2006 22:54, Nicolas Boulay wrote: > Le mardi 18 Avril 2006 22:33, Lourens Veen a écrit : > > On Tuesday 18 April 2006 16:16, Timothy Miller wrote: > > > That is the basic idea behind MISC. Everything is done via > > > special-purpose registers. > > > > > > But as I said before, all you're really doing is encoding the > > > opcode into the register index. > > > > What if there is more than one adder, or multiplier? It's lower > > level than that, you don't just say which operation you want, but > > also where it should be executed. > > You could do that too with VLIW instruction world. You don't need out > of order execution.
What if all the functional units had the same latency, that is, they all have a fifo on their output that increases their latency to some common maximum M. Scheduling would become trivial, you just generate the instructions in order, and then interleave M copies of the code. There are always M identical instructions in a row so you only need to load a new instruction every M clock cycles. ILP could be achieved through having multiple MISC cores, if the compiler makes sure that they don't access the same functional unit at the same time. Lourens
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