Tom Cook wrote:
I don't know a lot about shaders; is floating point a "must" or would fixed point be possible? Fixed point would simplify the logic a good deal.
I think that you would need 64 bits for fixed to work. So with multiply it would actually be simpler to use 32 bit float. It appears to me that we would need 4 hardware multipliers and with 32 bit IEEE float, this is only 23 bits x 23 bits and you only need the 26 most significant bits of output to round the result so you don't need the whole 46 bit multiplier array. Other functions are an XOR for the sign, an 8 bit adder with overflow, and a minus 7FH circuit to set the exponent to the correct bias. This would certainly take less space in a FPGA than a 64 bit multiplier, probably less space than a 32 bit multiplier.
I believe that I read somewhere that IP for 32 bit float multiplier is available.
OTOH, it is true that an adder is more complicated since it needs a subtracter for the exponents, some sign logic, and two funnel shifters. Since you only use one shifter at a time you might be able to get by with only one and two multiplexers.
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