On Friday 09 June 2006 20:46, Petter Urkedal wrote: > Ryan Osial wrote: [deleted]
> /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:104:0:104:5: > note: Trying to extract state machine for register state > Extracted state machine for register state > State machine has 4 reachable states with original encodings of: > 00 > 01 > 10 > 11 > /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:90:4:90:10: > Only one always block may assign a given variable SCK_reg > Sorry. I don't read Verilog (Yet :). I've duplicated what you got here with ISPLever, and am trying to find my way through it (Mainly so I can try out the bits of ISPLever like block map etc so I can see what they look like). What exactly doesn't it like about the code? Is it somply complaining because there's two (Almost) identical always blocks always @(posedge clock) SCK_reg <= #1 1; always @(negedge clock) SCK_reg <= #1 CE_; Which both assign to SCK_reg? In which case it doesn't seem to understand that (presumably) SCK_reg should be assigned 1 on the rising edge of the clock, and CE_ on the falling edge... Do I read it correctly? And what should be the way to specify an action on the rising or falling edge of the clock in verilog? [Sorry. Just wondering really if I'm reading this correctly]. In addition, should we be doing anything with the WP and HOLD pins of the SPI? They don't seem to be defined as an output for the module like the other SPI input pins... Is hold simply to be tied and WP jumpered? Or something else? Hamish. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
