On 6/13/06, Hamish <[EMAIL PROTECTED]> wrote:


Sorry. Maybe I'm being thick tonight... But what are the columns? I can't find
how they relate to each other or what DQ Number, DQ pins, DQS pins mean.

Sorry.  I guess the pattern is less apparent than I thought.

We are driving pairs of 16-bit DDR chips together as a unit, so it's
basically like driving a single 32-bit chip.

For each group of 8 data lines (DQ), there is:
A single data strobe (DQS) that is just a data clock and;
A single data mask (DM) that is a byte-enable for writes.

Each pair of chips has a single set of control lines (address, ras,
cas, we(wr), bank, pclock, and nclock).

The ECP2 places restrictions on how many DQ lines can be associated
with each DQS.  See, it has specialized DDR memory hardware that we're
taking advantage of.  Due to the fact that we have to use all of the
pins on the package, we had to play fast and loose with that
arrangement of DQ and DQS signals.  So rather than going according to
the ECP2 spec and associating a given group of 8 DQ's with a
particular DQS, we have instead associated a given group of 32 DQ's
with the corresponding group of four DQS's.  That is, DQ's are not
balanced with respect to DQS's, but they're matched up in a macro
group.  This means the two chips are stuck working in unison, but
that's okay, because the shared control lines create the same
restriction.


Also what software was used to create the schematic in the first place? Why
can't we export the data from there in a format that could be massaged with a
quick script?

It's in Veribest, a proprietary tool, and it was entered via schematic
capture.  There's a possibility that we could export it, but there's
little point because it would just steal time from Howard and not
speed us up much.

Besides, any such export would just associated the physical pins with
their logical names on the schematic, but that wouldn't group them in
any meaningful way.
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