On 6/20/06, Jack Carroll <[EMAIL PROTECTED]> wrote:
Somebody pointed out to me yesterday that a mask set for a 250 nm
process isn't $2M, it's $50K. And that's on SOI, which is much faster than
a normal 250 nm process, because it eliminates isolation junction
capacitance.
How much logic is the TRV10 going to need? Could it be implemented
with an older CMOS or SOI process that doesn't have such prohibitive
up-front costs?
I'l have to let Howard answer this one. He contacted ASIC vendors and
priced them out. If I understand it correctly, your $50k NRE costs
less up front but more in the long run. Oh, and it's not $2M for the
NRE. It's $2M for a 100k unit production run.
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