I'm a sucker for press, so I thought this might be interesting. Tell me what you think. This is just a concept, so I'm sure it's missing lots of stuff.
Open Graphics Project releases novel video timing controller design under GPL While gearing up for the imminent release of OGD1 [url], their FPGA-based development platform, members of the Open Graphics Project [url] have gotten to work on some elements of their graphics chip design that users of OGD1 will also need to make that board minimally functional. Written in Verilog, a hardware description language, these pieces include video control, memory control, and the PCI interface. Since OGD1 is also designed to be a general purpose prototyping board, engineers will find these pieces to be very helpful, even critical, to getting their designs up and running. The most recent release is the video controller. Video signals are usually transmitted in frames, each frame being a still image from a slice in time. Each frame is divided up vertically into scanlines, and the scanlines are divided horizontally into pixels. Synchronization signals accompany the video signal, indicating to the monitor the beginning of the frame and the beginning of each scanline. This way, a rectangular image can be transmitted linearly and reconstructed by the monitor on the screen. A simple progressive-scan video controller would consist of two counters and some configuration registers. The horizontal counter would count pixels on the scanline, with configuration registers indicating when the sync signals are to be asserted and when active video is to be transmitted. Similarly, a vertical counter would count scanlines, with configuration registers indicating the vertical sync and end of the frame. But as you start adding features, like interlacing, panning, and TV compatibility, the video controller logic gets increasingly complicated. In an effort to minimize chip area, the OGP designers decided to do away with the standard design and trade logic gates for memory cells. Vaguely reminiscent of "display lists" from some old 8-bit computers, the OGP video controller reminds one of a general-purpose CPU. Each "instruction" executed by this CPU-like video controller corresponds to a block of four pixels on the video display. In order to display a video image, one can write a sort of program that is executed by the controller. The main program handles the vertical control and syncs; for each scanline, subroutines are called to handle the horizontal syncs, fetches from video memory, and transmission of pixels. Programs for this video controller can get to be very complex, but driver developers would almost never see one of these programs, instead relying on a "video compiler" that takes standard timing numbers like in xorg.conf and generating the program automatically (whenever you change your screen resolution). The general idea is to have a very powerful and flexible but economical video controller design by offloading the complexity from the hardware to the software. Besides supporting just about any video format you want, this design also allows for entirely novel sorts of video signals, as well as irregular things like the VESA DPVL standard [url]. The latest design is checked into the OGP's subversion repository [url], ready to be simulated. The project could use some help with this from people willing to learn to use a Verilog simulator (like Icarus), code video control programs, and test the correctness of the video controller design. Currently, the controller comes with a simple test harness and a script to run the design through Icarus and bring up the results in GTKWave. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
