Timothy Miller wrote:
On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
OGD1 comes with 256MiB.
I presume that the bus width on OGC will be the same.
So, are we going to use "eight 128 megabit chips" on the OGC to
have a 128 bit buss?
256MiB is relatively cheap.
Yes. This isn't a problem. You just use either 128 MB or 256 MB chips.
Only power-consumption is any reason to use fewer chips.
Doesn't DDR2 use less power. Having scanned the data sheet, I find only
three major differences:
1. Start up is a different sequence.
2. Lower voltage (=lower power)
3. Shortest burst is 4
We should ensure OGA-based designs can use 1, 2, or 4 memory
controllers (i.e. pairs of chips), making the configurable bus widths
32, 64, or 128 bits.
I don't think that that is needed. Even $100 boards have 128 MB of
memory and a 128 bit video memory bus.
We should also support 32-bit wide chips if we can, but if we can't
adequately test that, it'll be considered an unsupported feature
unless we find it works perfectly on the ASIC.
I suppose that in the future the smaller chips will become obsolete and
it would be necessary use 32 bit chips to have "only" 256 MB of memory.
At the present time, using 32 bit chips would be needed to have only 64
MB of memory and still have a 128 bit bus.
We should spec OGA internally to have an address space of like 1GiB
so that it's somewhat scalable, but this is an after-thought.
That is probably a good idea since memory will keep going down in price.
--
JRT
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