2006/7/21, James Richard Tyrer <[EMAIL PROTECTED]>:
Timothy Miller wrote:
> On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
>> Timothy Miller wrote:
>> > On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
<...>
> With this design, we can get <fifo-length> requests ahead of the
> memory controller, absorbing pipeline and CAS latency, along with
> somewhat reducing the impact of row misses.
Are you talking about accessing the memory out of order? This isn't
going to be "simple". There is nothing that is going to absorb CAS
latency, and I don't see that getting ahead is necessary. Actually, I
was concerned that there might be a problem getting the address 4 to 6
clocks before the data was needed. I don't see that there is anything
that can be done about row misses without going to out of order memory
access.
Why is it not possible to interleave bank access ? If you access the
data linearly you could decide where the bank are coded inside the
adress bus and aborb CAS latency in this case.
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