Nicolas Boulay wrote:
2006/7/21, James Richard Tyrer <[EMAIL PROTECTED]>:
Timothy Miller wrote:
> On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
>> Timothy Miller wrote:
>> > On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
<...>
> With this design, we can get <fifo-length> requests ahead of the
> memory controller, absorbing pipeline and CAS latency, along with
> somewhat reducing the impact of row misses.
Are you talking about accessing the memory out of order? This isn't
going to be "simple". There is nothing that is going to absorb CAS
latency, and I don't see that getting ahead is necessary. Actually, I
was concerned that there might be a problem getting the address 4 to 6
clocks before the data was needed. I don't see that there is anything
that can be done about row misses without going to out of order memory
access.
Why is it not possible to interleave bank access ? If you access the
data linearly you could decide where the bank are coded inside the
adress bus and aborb CAS latency in this case.
Actually, you can. The question is whether it would be best. This
wouldn't make any difference in the length of the pipeline for memory
access -- it wouldn't help with CAS latency. You would activate a row
(in one of the 4 banks), enter a column address, and then wait the CAS
latency for the data part of that memory cycle. Actually, it looks like
this would add a clock to the pipeline length for the row address..
If you can keep reading (write impose an additional delay) on an active
row, you can pipeline the addresses. If you can issue a row address on
each clock, you can get data out every half clock. It is just that
there is a delay between the address and the data.
This method would hide some of the precharges. The common wisdom is
that this method is best if you have basically random access of memory
because you would use autoprecharge. The problem that I see is that it
the access was random that you would have 25% of a row miss on each
memory cycle. Other hand, sequential access wouldn't have any, but if
we have sequential access, we don't need this.
Did you download a data sheet for the memory and look at it?
http://download.micron.com/pdf/datasheets/dram/ddr/256MBDDRx4x8x16.pdf
This had diagrams that show how pipelining works.
--
JRT
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